Difference Set Codes Based Majority Logic Fault Detection
E.Jebamalar Leavline , F. Jabeena , M.Dhivyapriya, V.Kalaiyarasi
Abstract
Errors in memory applications such as SRAM, is increased now a days due to technology scaling, higher package density and lower voltages even at normal terrestrial environments. There are several techniques to detect and correct the errors. These techniques can only detect single error and double errors due to the low encoding and decoding complexity. It leads to longer decoding time and large power consumption. In majority logic decoding technique, different set cyclic codes are used for multierror detection/correction. DSCC is a part of LDPC (Low Density Parity Check) codes. Since this technique is independent of code size.
Fault Detection, Difference Set Codes, LDPC, SRAM.
[1] C. W. Slayman, “Cache and memory error detection, correction, and reduction techniques for terrestrial servers and workstations,” IEEE Trans. Device Mater. Reliabil., vol. 5, no 3, pp. 397–404, Sep. 2005.
[2] S. Satoh, Y. Tosaka, and S. A. Wender, “Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM’s,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 310–312, Jun. 2000.
[3] J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, “Characterization of multi-bit soft error events in advanced SRAMs,” in Int. Electro Devices Meeting (IEDM) Tech. Dig., Washington, DC, Dec. 2003, pp. 21.4.1–21.4.4.
[4] R. Koga, S. H. Penzin, K. B. Crawford, and W. R. Crain, “Single Event Functional Interrupt (SEFI) sensitivity in microcircuits,” in Proc. 4th Radiation and Effects Components and Systems (RADECS), Cannes, France, Sep. 1997, pp. 311–318.
[5] P. Ankolekar, S. Rosner, R. Isaac, and J. Bredow, “Multi-bit error correction methods for latency-contrained flash memory systems,” IEEE Trans. Device Mater. Reliabil., vol. 10, no. 1, pp. 33–39, Mar. 2010.
[6] Y. Kato and T. Morita, “Error correction circuit using difference-set cyclic code,” in Proc. ASP-DAC, 2003, pp. 585–586.
[7] Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications Shih-Fu Liu, Pedro Reviriego, Member, IEEE, and Juan Antonio Maestro, Member, IEEE
[8] S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2004
[9] H. Naeimi and A. DeHon, “Fault secure encoder and decoder for NanoMemory applications,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 4, pp. 473–486, Apr. 2009
[E.Jebamalar Leavline , F. Jabeena , M.Dhivyapriya, V.Kalaiyarasi (2015) Difference Set Codes Based Majority Logic Fault Detection IJIRCST Vol-2 Issue-6 Page No-91-94] (ISSN 2347 - 5552). www.ijircst.org
E.Jebamalar Leavline
Department of ECE, Bharathidasan Institute of Technology, Anna University, Tiruchirappalli – India, jebi.lee@gmail.com
