A Literature Review on Wishbone Bus Technique for Network on Chip Architecture

Mr. Arjun M M.; Mr. Kendaganna Swamy; Dr. Uma.B.V HOD & Professor

Abstract

The Network-on-Chip has been recognized as a paradigm to solve System-on-Chip (SoC) design challenges. The bus technologies is one of key researches of a NoC design. This is a review paper which gives an overview of different bus computer architectures (CAs) , called AMBA, Coreconnect and Wishbone. It starts with a brief introduction Network On Chip (NoC) , then looks at bus organizations , and concludes with a discussion related to a comparative performance analysis and also gives merits and demerits of all three bus architectures.

Keywords

SoC buses, NoC, AMBA, Coreconnect, Wishbon

References

[1] Milica Mitic and Mile Stojcv, “A Survey of Three System-onChip Buses AMBA, CoreConnect and Wishbone,” ICEST 2006.

[2] Bernini L. and De Micheli G., Networks on Chips. A New Paradigm for Component-based MpSoC Design, chapter 3 in Jerraya A.A. and Wolf W., (Eds.), Multiprocessor Systems-onChips, Elsevier, Amsterdam, pp. 49–80, 2005.

[3] Ho W.H. and Pinkston T.M., “A Design Methodology for Efficient Application-specific on-chip interconnects,” IEEE Trans. Parallel Distributed System, 17(2), pp. 174-179, February 2006.

[4] Richard Herveille, WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores, Open Cores Organi zation, rev. version: B4,2010.

[5] IBM Corp., USA,” CoreConnect bus Architecture,” 1999.

[6] Richard Herveille, WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores, rev. version: B4, 2010. By Open Cores Organization, p.7, 2010.

[7] Anurag Shrivastava, G.S. Tomar, and Ashutosh Kumar Singh, “Performance Comparison of AMBA Bus-Based System-On-Chip Communication Protocol,” International Conference on Communication Systems and Network Technologies, IEEE Computer Society, p. 449, 2011.

Cites this article as

M. A. M. M., M. K. S. , D. U. H. &. Professor, "A Literature Review on Wishbone Bus Technique for Network on Chip Architecture", International Journal of Innovative Research in Engineering & Management (IJIREM), Vol-2, Issue-4, Page No-5 - 8, 2015. Available from: